The present invention is directed to logic-level sensors, particularly sensors to be used in testing very fast digital circuitry.
A large number of the procedures employed in automatic test equipment for testing digital circuitry involve determining that a signal has reached one of two discrete logic levels by a predetermined time. The sensor for making the determination typically includes a comparator, which receives a reference level as one input and as its other input a signal from the circuit to be tested. The output of the comparator assumes a first level when the sensed voltage is greater than the reference voltage signal and assumes a second level when the sensed voltage is less than the reference voltage. The automatic test equipment inspects the comparator output at a predetermined time to determine whether the output of the circuit under test is at the right logic level.
In high-speed circuitry, the requirements are such that the time taken by the comparator for a transition of its output from one of its levels to the other is significant. The circuit under test may be required to reach a predetermined level at a certain time, but inspection of the comparator output must be delayed from that time because the comparator must be given time to change its output in response to the change in the output of the circuit under test. Accordingly, the tester must take the comparator delay into account and inspect the comparator output at a time delayed from the required transition time by the expected delay of the comparator.
For this reason, comparators used for this purpose are typically high-speed devices The high speed is desired for two reasons. One is that a shorter comparator delay results in a faster overall test. The second is that a faster comparator minimizes inaccuracies; the speed of a comparator transition depends to a certain extent on the amount by which the sensed signal differs from the reference signal, so the delay imposed by the comparator can vary. A faster comparator reduces the amount of variation caused by variations in input signal.
This requirement for fast comparators can result in significant increases in the cost of automatic test equipment. It is not uncommon for automatic test equipment to have two to three hundred test pins, and at least two comparators are typically required for each test pin. Thus, the comparator expense makes a significant contribution to the expense of the entire system.
It is accordingly an object of the present invention to achieve low, repeatable comparison times without using the high-cost comparators that such high-speed comparisons would ordinarily require.